Field effect transistors are required for many applications in silicon microelectronics.
In circuit technology, it is often desirable, in modern CMOS processes, to have a plurality of different n-MOS transistors and a plurality of different p-MOS transistors having different threshold voltages (so-called multi-VT technology, where VT denotes the threshold voltage of the transistor). For specific applications, it may be necessary to have transistors with a particularly high switching speed, whereas a minimal leakage current of the transistor is sought in other applications. If the multi-VT technology is combined with the use of different supply voltages VDD of an integrated circuit (multi-VDD/VT technology), then the optimum voltage swing may be selected, depending on the switching activity of a specific transistor of an integrated circuit, in order to achieve maximum boosting of the gate voltage VDD-VT. Examples of transistors having such requirements are transistors in clock circuits with high switching activity, a low voltage swing and a low threshold voltage. In the case of a transistor in a clock circuit, the leakage current is of relatively little relevance on account of the high activity, whereas minimizing the dynamic power loss (which is a function of the square of the supply voltage VDD) is of primary interest. By contrast, in logic circuits with relatively low activity (for example less than 30%), the static power loss on account of electrical leakage currents in the switched-off state is of greater relevance, so that transistors having a higher threshold voltage are advantageous here. In order not to impair the switching speed in the active state (the switching time tD is proportional to 1/[VDD-VT]) and in order to avoid an undesirable reduction of the boosting of the gate voltage, the supply voltage VDD of the logic block is increased correspondingly.
An overview of the multi-VDD/VT circuit technology, in particular with regard to conventional CMOS technology, is found for example in Hamada, M, Ootaguro, Y, Kuroda, T (2001) “Utilizing Surplus Timing for Power Reduction”, Proceedings of the IEEE Custom Integrated Circuits Conference 2001.
A central problem of conventional integrated circuits is the increasing deterioration of the electrical properties of MOS transistors (“metal oxide semiconductor”) with increasing structural fineness, that is to say miniaturization. This is caused for example by the punch-through effect, the latch-up effect and also the parasitic capacitance between the drain/source region and the substrate, the parasitic capacitance greatly increasing more than proportionally in relation to the transistor size. The term punch-through effect refers to an undesirable punch-through of current between adjacent transistors of a transistor arrangement. The term latch-up effect designates the phenomenon wherein a transistor of the p conduction type and a transistor of the n conduction type, when the distance between them falls below a minimum distance, may form a parasitic thyristor at which a high triggering current may flow, which may effect a local destruction of an integrated semiconductor component.
The problems described are alleviated in the case of SOI technology (“silicon-on-insulator”), which uses a silicon layer on a silicon oxide layer on a silicon substrate as basic material for forming an integrated circuit. The problems described can be alleviated particularly with the use of a thin layer of silicon (e.g. having a thickness of 20 nm) on an electrically insulating silicon oxide layer.
Furthermore, using a doped substrate may give rise to the problem that technologically dictated local fluctuations in the dopant concentrations give rise to a variation of the threshold voltage in different transistors of an integrated circuit. This problem is avoided when an undoped substrate is used.
However, if a thin undoped silicon layer is used as a base layer for forming a field effect transistor, then it is not possible to alter the threshold voltage of the field effect transistor by setting the doping of the channel region. In this case, the threshold voltage of a field effect transistor may be defined by defining the work function of the material of the gate region. In this case, a separate gate material is in each case required for each type of transistor (low-power transistor or high-performance transistor, p-MOS transistor or n-MOS transistor), the threshold voltage of the respective transistor being defined by selection of the gate material.
However, the free material selection of the gate regions of different transistors of an integrated circuit may be restricted for technological reasons. Furthermore, it is complicated and therefore expensive to use different gate materials in a method for producing an integrated circuit with different transistors.
Thin-film SOI transistors (“silicon-on-insulator”) are of interest particularly in the case of a CMOS technology with dimensions below 50 nm. As discussed for example in Schiml, T, Biesemans, S, Brase, G, Burrell, L, Cowley, A, Chen, KC, Ehrenwall, A, Ehrenwall, B, Felsner, P, Gill, J, Grellner, F, Guarin, F, Han, LK, Hoinkis, M, Hsiung, E, Kaltalioglu, E, Kim, P, Knoblinger, G, Kulkarni, S, Leslie, A, Mono, T, Schafbauer, T, Schroeder, P, Schruefer, K, Spooner, T, Towler, F, Warner, D, Wang, C, Wong, R, Demm, E, Leung, P, Stetter, M, Wann, C, Chen, JK, Crabbe, E (2001) “A 0.13 μm CMOS Platform with Cu/Low-k Interconnects for System On Chip Applications” 2001 Symposium on VLSI Technology, Digest of Technical Papers, in view of the high diversity of components, a plurality of different types of transistor are required for the logic in existing processes of the 130 nm technology. In the case of three different types of transistor with different threshold voltages (high threshold voltage, medium threshold voltage, low threshold voltage) and also in the case of two different types of charge carrier (n-MOS transistor, p-MOS transistor) a total of six different materials result for the gate region. An associated thin-film SOI-CMOS process therefore requires a very high process complexity.
In present-day CMOS technologies, the threshold voltage of the field effect transistors used therein is generally set by doping the channel region. Such implantations include forming LDD regions (“Lightly Doped Drain”), carrying out a pocket doping (localized doping of the region between the source/drain regions or in the channel region, thereby reducing the sensitivity of the transistor to technologically dictated fluctuations in the length of the gate region), and also forming a retrograde well (clearly a highly doped region within the substrate between the source/drain regions). However, these implantations are subject to technologically dictated fluctuations, which result in undesirable fluctuations of the transistor properties. Furthermore, particularly in the case of fully depleted thin-film SOI transistors primarily in the case of technology nodes with feature dimensions of less than 50 nm, it is no longer possible to employ this method for setting the threshold voltage since the doping-dependent contribution to the threshold voltage VTdop is proportional to q*NA*tsi. In this case, tsi designates the thickness of the silicon layer, NA designates the dopant concentration in the channel region, and q designates the electrical elementary charge. For tsi<20 nm and NA<1016 cm−3, VTdop then has hardly any influence on the threshold voltage.
The alternative to setting the threshold voltage by means of targeted doping consists in using a plurality of different gate materials for transistors with different threshold voltages and also different conduction types. However, thin-film SOI-CMOS processes that permit the formation of MOS transistors with different threshold voltages do not exist at the present time.
One possibility for setting the transistor properties in SOI technology is the use of transistors having different lengths of the gate region, since the length of the gate region also has a crucial influence on the threshold voltage of a field effect transistor. A capability for sufficiently exact setting of the threshold voltage of transistors by setting the length of the gate region presupposes a sufficiently good resolution of a masking technique.
FIG. 1A shows an SOI field effect transistor 100 in a technology with a minimum feature dimension that can be achieved of F=150 nm. The SOI transistor 100 has a silicon substrate 101, a silicon dioxide layer 102 arranged on the silicon substrate 101, and an undoped silicon layer 103 arranged on the silicon dioxide layer 102. The layers 101 to 103 form an SOI layer. A first source/drain region 106 is implanted in a first surface region of the undoped silicon layer 103, and a second source/drain region 107 is implanted in a second surface region of the undoped silicon layer 103. A region between the two source/drain regions 106, 107 of the undoped silicon layer 103 forms the channel region 108. In FIG. 1A, the lateral extent of the gate region 104 is determined by the smallest feature dimension that can be achieved in the technology generation, F=150 nm. A typical value for the inaccuracy during patterning is designated by AF in FIG. 1A. An accuracy of approximately ΔF=±20 nm can be achieved with the best patterning methods existing at the present time (electron beam lithography).
FIG. 1B shows a field effect transistor 110 of a technology generation in which the minimum feature dimension that can be achieved is F=50 nm. Assuming that the best resolution achieved at the present time is ΔF=20 nm, then it can be discerned that with conventional masking techniques, when striving for technology generations of 50 nm or less the uncertainties in the accuracy of the mask are too large to set the length of the gate region or the length of the channel region with sufficient accuracy. The relative accuracy when setting the length of the gate region in a technology generation where F=50 nm and with an uncertainty of ΔF=20 nm is 40%.
Therefore, as feature dimensions decrease further, with conventional masking technology, the threshold voltage of a transistor cannot be set with satisfactory accuracy by setting the length of the gate region. Moreover, the costs are very high when using masks. Furthermore, the production time of transistors increases more and more as masks become finer.
U.S. Pat. No. 5,532,175 discloses a method for adjusting a threshold voltage for a semiconductor device on an SOI substrate, in which a threshold voltage adjusting implantation is carried out.
Nuernbergk, D M et al. (1999) “Mache mögen's heiβ—Silicon on Insulator Bauelemente und ihre Besonderheiten”, in: “Mikroelektronik und Fertigung”, pages 61 to 64, discloses an overview of silicon-on-insulator components and their particular properties.
DE 198 23 212 A1 discloses a semiconductor device in which a field-shielding gate oxide layer is thicker at an edge section of a field-shielding gate electrode below a sidewall oxide layer.
DE 198 57 059 A1 discloses an SOI component and a method for producing it, in which the effect of a body at floating potential is reduced.
U.S. Pat. No. 5,273,915 discloses a method for producing bipolar junctions and MOS transistors on SOI.